Non-volatile memory devices and especially solid state memory devices tend to wear out over time. One main effect of such wear is the creation of errors in stored data. Different device types have different typical and industry accepted reliability, depending, for example, on the technology used and on the manufacturing process tolerance which can be achieved. Some flash controllers are designed capable of correcting errors up to a first (“weak”) bit error rate (for example up to 6-bits per 512 bytes) in a correctable group of memory cells having a standard size (for example 256 Bytes), while other controllers require a second bit error rate that is higher than the first bit error rate (for example up to 8-bits per 512 bytes) to obtain a stronger protection.
Several error handling schemes have been made in the art to provide a strong bit error rate protection using a weak error handling schemes. One solution is to split the group of memory cells to sub-groups (correctable groups) and to apply the existing, weaker error correction scheme on each sub-group separately. As such, each sub-group is individually protected by a weaker bit error rate. However, such error correction schemes require applying an error correction operation on each one of the sub group, thereby degrading the overall performance.
Another common approach is designing a new, stronger error correction scheme that is capable of correcting errors up to the desired bit error rate. The drawback of a new designed system is high cost affect and the time it takes to design such a system.
Although each of the prior art error handling schemes provides some protection for defective memory locations, none of them are perfect. Some schemes require excessive resource and development time; some degrade the system's overall read performance; and others provide inadequate protection.